// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :  frame_check_256
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
`include "top_define.v"
`timescale 1ns/1ps 
//
// *********************************************************************
//Ö¡¼ì²âÄ£¿é£¬¼ì²âÖ¡ÊÇ·ñÎªÕýÈ·¸ñÊ½£¬ÈôÖ¡¸ñÊ½²»ÕýÈ·Ôò½«²»ÕýÈ·µÄÖ¡¶ªÆú
//ÕýÈ·Ö¡¸ñÊ½£ºÏÈÓÐsop&&dval£¬ÒÔ´Ë×÷ÎªÖ¡µÄÆðµã£¬ºóÓÐeop&&dval£¬ÒÔ´Ë×÷ÎªÖ¡µÄÖÕµã
//´íÎó¸ñÊ½£º	1¡¢Î´¼ì²âµ½ÓÐÐ§µÄsop&&dval
//			2¡¢¼ì²âµ½ÓÐÐ§µÄsop&&dvalµ«ÊÇÎ´¼ì²âµ½eop&&dval£¬Çé¿öÏ¸·ÖÎª
//				2.1¡¢Ö¡¹ý³¤£¬ÓÐeopÓÐsop
//				2.2¡¢±íÏÖÎªÁ¬ÐøµÄÁ½¸ösopÐÅºÅ			
//²ÎÊý W_SIZE£ºÎ»¿í(8µÄÕûÊý±¶) MODE_SIZE£ºpkt_mod¿í¶È
module frame_check_256 (
	pkt_clk,
	rst_n,
    ram_2p_cfg_register,
	pkt_sop_i,
	pkt_eop_i,
	pkt_dval_i,
	pkt_data_i,
	pkt_mod_i,
	frame_check_rdy,
	pkt_eop_o,
	pkt_sop_o,
	pkt_dval_o,
	pkt_data_o,
	pkt_mod_o,
	pkt_dsav_o,
	ram_full
	// error_frame_o
	);
//ÊäÈë¿Éµ÷Õû²ÎÊý Î»¿íÐ¡ÓÚµÈÓÚ256
parameter W_SIZE 		= 	256				;
parameter MODE_SIZE		= 	5 				;//	size of MODE (3 if 64,4 if 128, 5 if 256)
parameter PTR 			= 	8 				;// address width of FIFO (3 if 8,4 if 16,5 if 32)
parameter DEPTH 		= 	144 			;
parameter DEPTHminus1  =	DEPTH - 1 		; 
parameter DEPTH2minus1  =	DEPTH * 2 - 1 	; 
//¼ÆËã²ÎÊý²»¿Éµ÷Õû
parameter W_SIZE_BYTE 	= 	W_SIZE/8		;// size of FIFO word (8, 16, 24 or 32)
parameter A_FULL 		=   200 			;



//input
input 							pkt_clk 		;
input 							rst_n 			;
input [9:0]                     ram_2p_cfg_register;
//data_input		
input 							pkt_sop_i 		;
input 							pkt_eop_i 		;
input 							pkt_dval_i 		;
input [(W_SIZE-1):0]			pkt_data_i 		;
input [(MODE_SIZE-1):0]			pkt_mod_i 		;

input 							frame_check_rdy ;
//data_output
output reg 						pkt_sop_o 		;
output reg 						pkt_eop_o 		;
output reg 						pkt_dval_o 		;
output reg [(W_SIZE-1):0] 		pkt_data_o 		;
output reg [(MODE_SIZE-1):0] 	pkt_mod_o 		;
output reg  					pkt_dsav_o 		;

// output [10:0] 					error_frame_o 	;
output reg 						ram_full 		;

//*************************************

reg 							pkt_sop_reg 		;
reg 							pkt_eop_reg 		;
reg 							pkt_dval_reg 		;
reg [(W_SIZE-1):0]				pkt_data_reg 		;
reg [(MODE_SIZE-1):0]			pkt_mod_reg 		;
//ÀûÓÃË«¶Ë¿Úram½øÐÐÖ¡µÄ´æ´¢	
reg [10:0]  					frame_cnt 			;
reg [10:0]						frame_cnt_new 		;//×éºÏÂß¼­ÏÈËãºÃ½á¹û£¬Í¬²½µçÂ·¸üÐÂµ½frame_cnt
(*mark_debug = "true"*)reg	[ 5:0] 						ram_cnt				;//¼ÇÂ¼ramÖÐÎ´¶Á³öµÄÖ¡¸öÊý£¬Î»¿í¿Éµ÷
(*mark_debug = "true"*)reg  							w_success 			;//³É¹¦½«Ö¡Ð´Èëram
(*mark_debug = "true"*)wire 							r_success 			;//³É¹¦½«Ö¡¶Á³öram
wire [6:0] 						r_res_len_cnt 		;
(*mark_debug = "true"*) reg [ 6:0] 						r_res_len_cnt_reg 		;	 		
(*mark_debug = "true"*) reg [ 6:0] 						w_res_len_cnt 			;//¼ÆËãµ±Ç°Ö¡Ö¡¼ä¸ô
(*mark_debug = "true"*) reg 							w_res_len_cnt_en		;
(*mark_debug = "true"*) reg 							w_res_len_cnt_en_dl 	;
(*mark_debug = "true"*) reg 							r_res_len_cnt_en 		;
(*mark_debug = "true"*) wire 							res_update_flag 		;
(*mark_debug = "true"*) wire  							rd_cnt_update_flag 		;
(*mark_debug = "true"*) reg  							rd_cnt_update_flag_dl	;
(*mark_debug = "true"*) wire 							res_len_cnt_empty 		;
(*mark_debug = "true"*) reg 							res_len_cnt_empty_dl	;

//Ö¡Ð´Èëram	
(*mark_debug = "true"*) reg	[PTR:0]						addr_start_w	;//¼ÇÂ¼µ±Ç°Ö¡¿ªÊ¼µÄÎ»ÖÃ
// (*mark_debug = "true"*) reg	[PTR-1:0]					addr_start_w_in	;//¼ÇÂ¼µ±Ç°Ö¡¿ªÊ¼µÄÎ»ÖÃ
(*mark_debug = "true"*) reg	[PTR:0] 					ram_waddr 		;
// (*mark_debug = "true"*) reg	[PTR-1:0] 					ram_waddr_in 	;
(*mark_debug = "true"*) reg [PTR:0] 					ram_cnt_wr 		;
(*mark_debug = "true"*) reg [W_SIZE+MODE_SIZE+1:0] 		ram_wdata 		;
// reg [W_SIZE+MODE_SIZE+1:0] 		ram_wdata_reg 	;
(*mark_debug = "true"*) reg 							ram_wen 		;// Ð´Èë¶Ë¿ÚÐ´Ê¹ÄÜÐÅºÅ
(*mark_debug = "true"*) reg 							sop_flag 		;
//Ö¡Ð´Èëram
(*mark_debug = "true"*) reg	 [PTR:0] 					ram_raddr 		;
(*mark_debug = "true"*) reg	  							ram_ren 		;
// (*mark_debug = "true"*) reg	 [PTR-1:0] 					ram_raddr_in 	;
(*mark_debug = "true"*) wire [W_SIZE+MODE_SIZE+1:0] 	ram_rdata 		;
(*mark_debug = "true"*) reg  [W_SIZE+MODE_SIZE+1:0] 	ram_rdata_reg 	;
(*mark_debug = "true"*) reg  [W_SIZE+MODE_SIZE+1:0] 	ram_rdata_reg_dl;
// reg 							ram_rden 	 	;
(*mark_debug = "true"*) reg 							ram_rdata_val 	;

(*mark_debug = "true"*) reg  [6:0] 						res_cnt_rd 		;  
(*mark_debug = "true"*) reg  [6:0]						res_cnt 		;
(*mark_debug = "true"*) reg  [6:0] 						rd_cnt 			;
(*mark_debug = "true"*) reg  							rd_cnt_dl 		;	

(*mark_debug = "true"*) wire 							tx_ready		;

always @(*) begin
	ram_cnt_wr = ram_waddr - ram_raddr + 'b1;
	if(ram_cnt_wr >= A_FULL)
		ram_full = 1'b1;
	else 
		ram_full = 1'b0;
end

//***********************Ð´Êý¾Ý****************************
//¶ÔÊäÈëÊý¾Ý½øÐÐ´òÅÄ»º´æ
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		pkt_sop_reg  	<=   1'b0;
 		pkt_eop_reg  	<=   1'b0;
 		pkt_dval_reg 	<=   1'b0;
 		pkt_data_reg 	<= 256'b0;
 		pkt_mod_reg  	<=   5'b0;
	end
	else begin
		pkt_sop_reg  	<= pkt_sop_i ;
		pkt_eop_reg  	<= pkt_eop_i ;
		pkt_dval_reg 	<= pkt_dval_i;
		pkt_data_reg 	<= pkt_data_i;
		pkt_mod_reg  	<= pkt_mod_i ;
	end
end
//Ð´Êý¾ÝÊ±Ö»Ð´ÕýÈ·µÄÖ¡
//Óöµ½sopÐÅºÅÊ±addr´Óaddr_start¿ªÊ¼Ð´Èë£¬Óöµ½eopÊ±¸üÐÂaddr_start
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		ram_waddr <= 9'b0;
	end
	else if (pkt_sop_reg && pkt_dval_reg && (~ram_full)) begin
		ram_waddr <= addr_start_w;
	end
	else if (frame_cnt_new > 11'd1518 && pkt_dval_reg) begin
		ram_waddr <= ram_waddr;
	end
	else if(pkt_dval_reg && sop_flag) begin
		// if(ram_waddr == DEPTH2minus1) begin
		// 	ram_waddr <= 9'b0;
		// end
		// else begin
			ram_waddr <= ram_waddr + 9'd1;
		// end	
	end
	else begin
		ram_waddr <= ram_waddr;
	end
end

// always @(posedge pkt_clk or negedge rst_n) begin
// 	if (~rst_n) begin
// 		// reset
// 		ram_waddr_in <= 8'b0;
// 	end
// 	else if (pkt_sop_reg && pkt_dval_reg && (~ram_full)) begin
// 		ram_waddr_in <= addr_start_w_in;
// 	end
// 	else if (frame_cnt_new > 11'd1518 && pkt_dval_reg) begin
// 		ram_waddr_in <= ram_waddr_in;
// 	end
// 	else if(pkt_dval_reg && sop_flag) begin
// 		if(ram_waddr_in == DEPTHminus1) begin
// 			ram_waddr_in <= 8'b0;
// 		end
// 		else begin
// 			ram_waddr_in <= ram_waddr_in + 8'd1;
// 		end	
// 	end
// 	else begin
// 		ram_waddr_in <= ram_waddr_in;
// 	end
// end

always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		ram_wdata 		<=  'b0;
		ram_wen 		<= 1'b0;
		w_res_len_cnt 	<= 7'b0;
	end
	else if (frame_cnt_new > 11'd1518 && pkt_dval_reg) begin
		ram_wdata 		<=  'b0;
		ram_wen 		<= 1'b0;
		w_res_len_cnt 	<= 7'b1;
	end	
	else if(pkt_dval_reg && pkt_sop_reg && (~ram_full)) begin
		ram_wdata 		<= {pkt_sop_reg,pkt_eop_reg,pkt_mod_reg,pkt_data_reg};
		ram_wen   		<= 1'b1;
		w_res_len_cnt 	<= 7'b1;
	end
	else if(pkt_dval_reg && sop_flag) begin
		ram_wdata   <= 	{pkt_sop_reg,pkt_eop_reg,pkt_mod_reg,pkt_data_reg};
		ram_wen 	<=	1'b1;
		w_res_len_cnt[5:0]	<= w_res_len_cnt[5:0] + 6'd1;
		if(pkt_eop_reg && (|pkt_mod_reg)) begin
			w_res_len_cnt[6] <= 1'b1;
		end
		else begin
			w_res_len_cnt[6] <= 1'b0;
		end
	end
	else begin
		ram_wdata   	<= 'b0;
		ram_wen 		<= 1'b0;
		w_res_len_cnt 	<= w_res_len_cnt;
	end
end

//sop_flag±íÃ÷ÒÑ¾­Óöµ½ÁËsopÇÒÃ»Óöµ½eop
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		sop_flag <= 1'b0;
	end
	else if (pkt_sop_reg && pkt_dval_reg && (~ram_full)) begin
		sop_flag <= 1'b1;
	end
	else if(pkt_eop_reg && pkt_dval_reg) begin
		sop_flag <= 1'b0;
	end
	else begin
		sop_flag <= sop_flag;
	end
end
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		w_success 			<= 1'b0;
		w_res_len_cnt_en 	<= 1'b0;
	end
	else if (sop_flag && pkt_eop_reg && pkt_dval_reg && (frame_cnt_new <= 11'd1518)) begin
		w_success 			<= 1'b1;
		w_res_len_cnt_en 	<= 1'b1;	
	end
	else begin
		w_success 			<= 1'b0;
		w_res_len_cnt_en 	<= 1'b0;
	end
end

// assign w_success = sop_flag && pkt_eop_reg && pkt_dval_reg && (frame_cnt_new <= 11'd1518);
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		addr_start_w <= 'b0;
	end
	else if (w_success) begin
		// if(ram_waddr == DEPTH2minus1) begin
		// 	addr_start_w <= 'b0;
		// end
		// else begin
			addr_start_w <= ram_waddr + 'd1;
		// end
	end
	else begin
		addr_start_w <= addr_start_w;
	end
end
// always @(posedge pkt_clk or negedge rst_n) begin
// 	if (~rst_n) begin
// 		// reset
// 		addr_start_w_in <= 'b0;
// 	end
// 	else if (w_success) begin
// 		if(ram_waddr_in == DEPTHminus1) begin
// 			addr_start_w_in <= 'b0;
// 		end
// 		else begin
// 			addr_start_w_in <= ram_waddr_in + 'd1;
// 		end
// 	end
// 	else begin
// 		addr_start_w_in <= addr_start_w_in;
// 	end
// end
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		w_res_len_cnt_en_dl <= 1'b0;
	end
	else begin
		w_res_len_cnt_en_dl <= w_res_len_cnt_en;
	end
end

// assign  frame_cnt_new = frame_cnt + ((pkt_eop_reg && pkt_dval_reg)?pkt_mod_reg:W_SIZE_BYTE);
always @(*) begin
	if (pkt_eop_reg & pkt_dval_reg) begin
		frame_cnt_new = frame_cnt + pkt_mod_reg;
	end
	else begin
		frame_cnt_new = frame_cnt + W_SIZE_BYTE;
	end
end


always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		frame_cnt <=  11'b0;
	end
	else if (pkt_sop_reg && pkt_dval_reg) begin
		frame_cnt <= W_SIZE_BYTE;
	end
	else if (pkt_eop_reg && pkt_dval_reg) begin
		frame_cnt <=  11'b0;
	end
	else if (frame_cnt > 11'd1518) begin
	//Ö¡¹ý³¤³¬³ö1518
		frame_cnt <= frame_cnt;
	end
	else if(pkt_dval_reg) begin
		frame_cnt <= frame_cnt_new;
	end
	else begin
		frame_cnt <= frame_cnt;
	end
end

//************************¶ÁÊý¾Ý*************************
//¶ÁÊý¾ÝÊ±ÒÔram_cntÎªÐÅºÅ£¬ram_cnt±íÊ¾ramÖÐ´æÓÐ¶àÉÙÕýÈ·µÄÖ¡Ã»ÓÐ¶ÁÈ¡

assign tx_ready = (frame_check_rdy | pkt_dval_o);

always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		ram_raddr <= 9'b0;
	end
	//ÐèÒª×¢Òârd_cnt±ä»¯Ê±¼ä
	else if(tx_ready && (|rd_cnt)) begin
		// if(ram_raddr == DEPTH2minus1)begin
		// 	ram_raddr <= 9'b0;
		// end
		// else begin
			ram_raddr <= ram_raddr + 9'd1;
		// end
	end
	else begin
		ram_raddr <= ram_raddr;
	end
end

// always @(posedge pkt_clk or negedge rst_n) begin
// 	if (~rst_n) begin
// 		// reset
// 		ram_raddr_in <= 8'b0;
// 	end
// 	//ÐèÒª×¢Òârd_cnt±ä»¯Ê±¼ä
// 	else if(tx_ready && (|rd_cnt)) begin
// 		if(ram_raddr_in == DEPTHminus1)begin
// 			ram_raddr_in <= 8'b0;
// 		end
// 		else begin
// 			ram_raddr_in <= ram_raddr_in + 8'd1;
// 		end
// 	end
// 	else begin
// 		ram_raddr_in <= ram_raddr_in;
// 	end
// end

always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		ram_ren <= 1'b0;
	end
	//ÐèÒª×¢Òârd_cnt±ä»¯Ê±¼ä
	else if(ram_raddr[7:0] == ram_waddr[7:0]) begin
		ram_ren <= 1'b0;
	end
	else begin
		ram_ren <= 1'b1;
	end
end


always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		ram_rdata_val  	<= 1'b0;
		ram_rdata_reg  	<= 263'b0;
		ram_rdata_reg_dl <= 263'b0;
		pkt_dval_o 	  	<= 1'b0;
	end	
	else begin
 		ram_rdata_val <= (|rd_cnt);
 		ram_rdata_reg <= ram_rdata;
 		if(tx_ready) begin
			pkt_dval_o 			<= ram_rdata_val;
			ram_rdata_reg_dl	<= ram_rdata_reg;
		end
		else begin
			pkt_dval_o  <= 1'b0;
			ram_rdata_reg_dl <= ram_rdata_reg_dl;
		end
	end
end


always @(*) begin
	if (tx_ready) begin
		// reset
		{pkt_mod_o,pkt_data_o} = ram_rdata_reg[260:0];
		pkt_eop_o = ram_rdata_reg[261] & pkt_dval_o;
		pkt_sop_o = ram_rdata_reg[262] & pkt_dval_o;
	end	
	else begin
		{pkt_mod_o,pkt_data_o} = ram_rdata_reg_dl[260:0];
		pkt_eop_o = ram_rdata_reg_dl[261] & pkt_dval_o;
		pkt_sop_o = ram_rdata_reg_dl[262] & pkt_dval_o;
	end
end


always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		pkt_dsav_o <= 1'b0;
	end
	else if (pkt_sop_o) begin
		pkt_dsav_o <= 1'b0;
	end
	else if (rd_cnt_update_flag_dl) begin
		pkt_dsav_o <= 1'd1;
	end
	else begin
		pkt_dsav_o <= pkt_dsav_o;
	end
end

//**************ram_cnt¿ØÖÆ******************
assign r_success = (~(|rd_cnt)) && (rd_cnt_dl);
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		ram_cnt <= 6'b0;
	end
	else if (w_success && (~r_success)) begin
		ram_cnt <= ram_cnt + 6'd1;
	end
	else if(r_success && (~w_success)) begin
		ram_cnt <= ram_cnt - 6'd1;
	end
	else begin
		ram_cnt <= ram_cnt;
	end
end

//***********rd_cnt res_cnt¿ØÖÆ*****************
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		r_res_len_cnt_reg 		<= 7'b0;
		res_len_cnt_empty_dl 	<= 1'b0;
	end
	else begin
		r_res_len_cnt_reg 		<= r_res_len_cnt;
		res_len_cnt_empty_dl 	<= res_len_cnt_empty;
	end
end
assign rd_cnt_update_flag = (~(|res_cnt[5:1])) && (|{ram_cnt[5:1],(rd_cnt_dl ^ ram_cnt[0])}) && (~(|rd_cnt)) && (!res_len_cnt_empty_dl);
always @(posedge pkt_clk or negedge rst_n) begin :res_cnt_update_dl
	if (~rst_n) begin
		// reset
		rd_cnt_update_flag_dl 	<= 1'b0;
	end
	else begin
		rd_cnt_update_flag_dl 	<= rd_cnt_update_flag;
	end
end
always @(posedge pkt_clk or negedge rst_n) begin :res_cnt_update
	if (~rst_n) begin
		// reset
		rd_cnt 	<= 6'b0;
	end
	else if (rd_cnt_update_flag) begin
		rd_cnt  <= r_res_len_cnt_reg[5:0];
	end
	else if((|rd_cnt) && tx_ready) begin
		rd_cnt  <= rd_cnt - 6'b1;
	end
	else begin
		rd_cnt 	<= rd_cnt;
	end
end

always @(posedge pkt_clk or negedge rst_n) begin 
	if (~rst_n) begin
		// reset
		res_cnt_rd			<= 6'b0;
		r_res_len_cnt_en 	<= 1'b0;
	end
	else if (rd_cnt_update_flag) begin
		if(r_res_len_cnt_reg[6]) begin
			res_cnt_rd			<= r_res_len_cnt_reg[5:0] - 6'b1;
		end
		else begin
			res_cnt_rd 			<= r_res_len_cnt_reg[5:0] + 6'b1;
		end
		r_res_len_cnt_en 	<= 1'b1;
	end
	else begin
		res_cnt_rd 			<= res_cnt_rd;
		r_res_len_cnt_en 	<= 1'b0;
	end
end

always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		rd_cnt_dl <= 1'b0;
	end
	else begin
		rd_cnt_dl <= (|rd_cnt);
	end
end

assign res_update_flag = ((~(|rd_cnt[5:1])) && rd_cnt[0] && tx_ready);
always @(posedge pkt_clk or negedge rst_n) begin
	if (~rst_n) begin
		// reset
		res_cnt 			<= 6'd0;
	end	
	else if (res_update_flag) begin
		res_cnt  			<= res_cnt_rd;
	end
	else if (|res_cnt) begin
		res_cnt 			<= res_cnt - 6'b1;
	end
	else begin
		res_cnt 			<= res_cnt;
	end
end

//Ë«¶Ë¿Úram Î»¿í=dataÎ»¿í+modÎ»¿í+sop+eop 
//Éî¶È¿ÉÒÔ¸ù¾Ýframe_cnt_new·ÂÕæºóµ÷Õû£¬µ«ÊÇÉî¶ÈÎª2µÄÕûÊýÃÝ
`ifdef ASIC
ram_2p_d256_w263_wrapper U_ram_2p_d256_w263_wrapper(
	.clk(pkt_clk),
    .ram_2p_cfg_register(ram_2p_cfg_register),
	.wren(ram_wen),
	.waddr(ram_waddr[7:0]),
	.wdata(ram_wdata),
	.rden(ram_ren & tx_ready),
	.raddr(ram_raddr[7:0]),
	.rdata(ram_rdata)
	);
fifo_fwft_nw64_nb7 U_fifo_fwft_nw64_nb7(
	.clk(pkt_clk),
	.clr(rst_n),
    .ram_2p_cfg_register(ram_2p_cfg_register),
	.w_data(w_res_len_cnt),
	.w_we(w_res_len_cnt_en_dl),
	.w_full(),
	.w_afull(),
	.r_data(r_res_len_cnt),
	.r_re(r_res_len_cnt_en),
	.r_empty(res_len_cnt_empty),
	.r_aempty()
	);

`else
mem_dp_nw256_nb263 U_frame_check_ram_256 (
	.addra 			(ram_waddr[7:0]			),
	.clka 			(pkt_clk				),
	.dina 			(ram_wdata				),
	.wea			(ram_wen				),
	.addrb 			(ram_raddr[7:0]			),
	.clkb 			(pkt_clk				),
	.enb 			(ram_ren 				),
	.doutb 			(ram_rdata 				)
	);

fifo_fwft_nw64_nb7 U_fifo_fwft_nw64_nb7(
	.clk 			(pkt_clk 				),
	.clr 			(~rst_n 				),
	.w_data 		(w_res_len_cnt 			),
	.w_we			(w_res_len_cnt_en_dl 	),
	.r_data 		(r_res_len_cnt 			),
	.r_re 			(r_res_len_cnt_en		),
	.w_full 		(),
  	.w_afull		(),
	.r_empty 		(res_len_cnt_empty 		),
	.r_aempty		()
	);
`endif


(*mark_debug = "true"*) reg [31:0] fc_in_cnt;
always @(posedge pkt_clk or negedge rst_n) begin
    if (~rst_n) begin
        fc_in_cnt <= 32'd0;
    end
    else if (pkt_dval_reg && pkt_eop_reg) begin
        fc_in_cnt <= fc_in_cnt + 32'b1;
    end
    else begin
        fc_in_cnt <= fc_in_cnt;
    end
end

(*mark_debug = "true"*) reg [31:0] fc_out_cnt;
always @(posedge pkt_clk or negedge rst_n) begin
    if (~rst_n) begin
        fc_out_cnt <= 32'd0;
    end
    else if (pkt_dval_o && pkt_eop_o) begin
        fc_out_cnt <= fc_out_cnt + 32'b1;
    end
    else begin
        fc_out_cnt <= fc_out_cnt;
    end
end

endmodule



